SX1303CTSXXXGW1
The LoRa® Corecell gateway Fine Timestamp reference design is a complete indoor and outdoor gateway turnkey solution reference design provided for US, EU and China ISM bands. The reference design is based on SX1303.
No evaluation kit available for purchase
Available reference design file package
Features
- Fine Timestamp
- 10x power reduction compared to legacy products
- Maximum TX output power (CN490) = +17dBm
- Maximum TX output power (EU868/US915) = +27dBm
- Receive 8 LoRa channels multi-data rates (SF5 ~ SF12 / 125 simultaneously kHz) + 2 mono-data rate (LoRa 250/500kHz and FSK 50kbps)
- Typical sensitivity level (CN490):
- -141dBm at SF12 BW 125kHz
- -12dBm at SF7 BW 125kHz
- -110dBm at FSK 50kbps
- Typical sensitivity level (EU868/US915):
- -140dBm at SF12 BW 125kHz
- -125dBm at SF7 BW 125kHz
- -110dBm at FSK 50kbps
- Home automation
- Building automation
- Factory automation
アプリケーション
Datasheets & Documentation
Additional Resources
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HAL & Packet Forwarder on Github
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関連情報
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今すぐ読むプロトタイプ作成と制作に役立ち、ダウンロード可能な豊富なリソースとデータシートを活用しましょう。
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